In high-speed electronic circuits, it is often necessary to generate one or more clock signals from a master clock signal. Each clock signal typically has a lower frequency than the master clock signal, and may have an asymmetrical duty cycle. To prevent timing errors in the circuits that operate in response to such clock signals, the timing of the edges where the clock signal changes state must be precise, and the edges must be fast so that the change of state occurs in a time that is short compared with the cycle time of the master clock signal.
One example of an application in which multiple clock signals, called sub-sampling clock signals, are derived from a master clock signal and in which the sub-sampling clock signals are required to have fast, precisely-timed edges is high-speed analog-to-digital conversion. Analog-to-digital converters can be characterized, in part, by a maximum conversion frequency that defines the maximum frequency at which the converter can perform digital conversions of an analog input signal. The cost of analog-to-digital converters increases sharply with increasing conversion frequency. When an analog input signal has to be converted at a high conversion frequency, it is often more economical to replace a single, fast, expensive analog-to-digital converter with a parallel analog-to-digital conversion system composed of multiple slower, cheaper analog-to-digital converters arranged in parallel. Moreover, even if cost is not a factor, conversion frequencies higher than that of the fastest single analog-to-digital converter can only be obtained using a parallel analog-to-digital conversion system.
When an analog-to-digital conversion system composed of N parallel analog-to-digital converters is used to generate a digital representation of an analog input signal, the effective conversion frequency is N times the conversion frequency of the individual analog-to-digital converters. FIG. 1 shows an example of an analog-to-digital conversion system 10 in which N=4. The analog-to-digital conversion system 10 is composed of the analog-to-digital converters 12, 13, 14 and 15, each preceded by a respective track-and-hold circuit 16, 17, 18 and 19, and the clock signal generator 28 that generates N sub-sampling clock signals. The analog input signal received by the analog signal input 20 is fed to the signal input of each of the track-and-hold circuits. The analog signal input of the track-and-hold circuit 16 is shown at 22. The track-and-hold circuits each include a clock signal input. Each track-and-hold circuit receives a different one of the sub-sampling clock signals through its clock signal input. The clock signal input of the track-and-hold circuit 16 is shown at 23.
The clock signal generator 28 derives the N sub-sampling clock signals from a master clock signal received through the master clock signal input 29. The master clock signal runs at the conversion frequency of the analog-to-digital conversion system 10, or at a multiple of this frequency.
The track-and-hold circuits 16-19 have analog signal inputs connected to the analog input 20. For example, the analog signal input 22 of the track-and-hold circuit 16 is connected to the analog input 20. The analog outputs of the track-and-hold circuits 16-19 are connected to the analog inputs of the analog-to-digital converters 12-15, respectively. For example, the analog output 24 of the track-and-hold circuit 16 is connected to the analog input 25 of the analog-to-digital converter 12. The digital outputs of the analog-to-digital converters 12-15 are connected to the digital output bus 27. For example, the digital output 26 of the analog-to-digital converter 12 is connected to the digital output bus 27.
The track-and-hold circuits 16-19 track the analog input signal received by the analog input 20 and sequentially hold values of the analog input signal at timings determined by the sub-sampling clock signals generated by the clock signal generator 28. The analog-to-digital converters 12-15 receive the analog samples taken by the track-and-hold circuits 16-19, respectively, and generate digital representations of the analog samples. The analog-to-digital converters transfer the digital representations to the digital output bus 27 to provide a serial or parallel bitstream.
The conversion frequency of the analog-to-digital conversion system 10 is equal to the frequency of the master clock signal, but each of the analog-to-digital converters 12-15 operates at a conversion frequency equal to 1/N of the frequency of the master clock signal. Consequently, each of the analog-to-digital converters can be simpler and less expensive than a single analog-to-digital converter that has a conversion frequency equal to the frequency of the master clock signal.
FIGS. 2A-2F illustrate the operation of the analog-to-digital conversion system 10 shown in FIG. 1. FIG. 2A shows the master clock signal received by the master clock signal input 29.
FIGS. 2B-2E show the sub-sampling clock signals generated by the clock signal generator 28 and fed to the clock signal inputs of the track-and-hold circuits 16, 17, 18 and 19, respectively. The clock signal generator sequentially generates the N sub-sampling clock signals with a delay of at least one cycle of the master clock signal between them. Each of the sub-sampling clock signals clocks one of the track-and-hold circuits 16-19 at 1/N of the frequency of the master clock signal. Consequently, the sub-sampling clock signals collectively clock the track-and-hold circuits at the conversion frequency of the analog-to-digital conversion system. In the example shown, each falling edge of the master clock signal causes one of the sub-sampling clock signals to change state, and causes the sub-sampling clock signal that changed state in response to the previous falling edge to revert to its original state. The changes in state of the sub-sampling clock signals are each delayed relative to the falling edges of the master clock signal by the propagation delay t.sub.d of the clock signal generator.
FIG. 2F shows the exemplary analog input signal 30 that is subject to conversion by the analog-to-digital conversion system 10. In this example, the analog input signal is a slow linear ramp to simplify the explanation, and the track-and-hold circuits 16-19 hold the level of the analog input signal when the rising edge of the respective sub-sampling clock signal reaches a level half-way between its low and high states. The sub-sampling clock signals shown in FIGS. 2B-2E are "ideal" sub-sampling clock signals in that they all have fast edges, and they all change state at timings having a fixed relationship to the master clock signal. As a result, consecutive analog samples 31, 32, 33 and 34 of the analog input signal 30 captured by the track-and-hold circuits 16-19, respectively, are at equal increments on the voltage scale V shown in FIG. 2F. The analog samples are then converted to digital representations by the analog-to-digital converters 12-15, respectively.
In practical embodiments of the analog-to-digital conversion system 10, a ring counter is conventionally employed as the clock signal generator 28. Ring counters are known in the art, and will therefore not be described in detail here. To generate N sub-sampling clock signals, a ring counter circuit composed of N counting stages is used. Although ring counters are capable of generating all of the sub-sampling clock signals with fast edges, this can only be achieved at the expense of high power consumption. Thus, in practical clock generator circuits employing a ring counter, at least some of the sub-sampling clock signals have slow edges. Moreover, the paths between the outputs of the counting stages and the track-and-hold circuits differ in length, and not all of the counting stages drive the same load. These factors impair the precision of the timing of the sub-sampling clock signals relative to the master clock signal.
FIGS. 2G-2I illustrate the effect of sub-sampling clock signals with slow edges and imprecise timing on the conversion accuracy of the analog-to-digital conversion system 10. In FIG. 2G, the edges of the sub-sampling clock signal fed to the track-and-hold circuit 19 change more slowly than the edges of the "ideal" sub-sampling clock signal shown in FIG. 2E. The edges of the "ideal" sub-sampling clock signal are indicated in FIG. 2G by broken lines. The slower edges of the sub-sampling clock signal cause the track-and-hold circuit 19 to hold the analog input signal 30 later than if it were clocked by the "ideal" sub-sampling clock signal shown in FIG. 2E. As a result, as shown in FIG. 21, the level of the analog sample 35 on the voltage scale V is different from than that of the analog sample 34. A conversion error can result when the analog-to-digital converter 15 converts this analog sample into a digital representation.
It should be mentioned that, in the example shown in FIG. 2G, the voltage level on the clock signal input required to switch the track-and-hold circuit 19 to its hold state is independent of the level of the analog input signal 30 to simplify the explanation. In many practical track-and-hold circuits, the voltage level on the clock signal input required to switch the track-and-hold circuit to its hold state depends on the level of the analog input signal. This effect may increase or decrease the sampling errors shown in FIG. 21. Whether the sampling error is increased or decreased depends on whether the analog input signal is changing in the same direction as, or the opposite direction to, the direction of the edge of the sub-sampling clock signal that switches the track-and-hold circuit to its hold state. When the analog input signal is a sine-wave, for example, this effect introduces harmonic distortion when the digital representations are converted back to an analog signal.
In FIG. 2H, the edges of the sub-sampling clock signal fed to the track-and-hold circuit 16 are delayed relative to the "ideal" sub-sampling clock signal shown in FIG. 2B. The edges of the "ideal" sub-sampling clock signal are indicated in FIG. 2H by broken lines. The delayed sub-sampling clock signal causes the track-and-hold circuit 16 to hold the analog input signal 30 later than if it were clocked by the "ideal" sub-sampling clock signal shown in FIG. 2B. As a result, as shown in FIG. 2I, the level of the analog sample 36 on the voltage scale V is greater than that of the analog sample 31. A conversion error can result when the analog-to-digital converter 12 converts this analog sample into a digital representation.
Thus, the conversion accuracy of an analog-to-digital conversion system composed of parallel analog-to-digital converters each preceded by a track-and-hold circuit depends on the speed and timing precision of the edges of the sub-sampling clock signals fed to the track-and-hold circuits. If the edges of the sub-sampling clock signal have imprecise timing or are slow, the analog input signal will be sampled at a time different from the time defined by the master clock signal. At the time defined by the edge of the sub-sampling clock signal, the value of the analog input signal will be different from its value at the time defined by the master clock signal, and an error in the analog sample will result. Errors in the analog samples cause conversion errors when the analog-to-digital converters convert the analog samples to digital representations.
Thus, what is needed in an analog-to-digital conversion system composed of N parallel analog-to-digital converters each preceded by a track-and-hold circuit is a clock signal generator capable of generating N sub-sampling clock signals whose edges are all substantially as fast as those of the master clock signal and that are precisely timed in relation to the edges of the master clock signal.
What is also needed in an analog sampling system composed of N parallel track-and-hold circuits is a clock signal generator capable of generating N sub-sampling clock signals whose edges are all substantially as fast as those of the master clock signal and that are precisely timed in relation to the edges of the master clock signal.
Finally, what is needed is a clock signal generator capable of generating N sub-sampling clock signals whose edges are all substantially as fast as those of the master clock signal and that are precisely timed in relation to the edges of the master clock signal.